1. Field of the Invention
The present disclosure relates to the field of electronic processing. More particularly, the present disclosure relates to register allocation and scheduling of program code.
2. Description of Related Art
Various applications can be implemented in the form of machine readable instructions stored in one or more storage devices and executed on associated hardware. Devices can be configured to perform a limited range of applications through embedded software executing on local hardware. Other devices can be general purpose devices on which applications can be configured through execution of software.
In typical applications, the software is developed in what is referred to as a high level language that can be relatively independent of the type of hardware used to execute the application. The high level language can be compiled or otherwise translated into hardware specific low level language instructions. The instructions can be loaded into a storage device, such as memory, and hardware can execute the instructions.
As programs evolve to require increasingly complex processes to be performed in ever decreasing time periods, the performance of hardware architectures eventually approach limitations that do not permit the near instantaneous execution of code desired of many applications. The program execution time is typically limited by an identifiable set of bottlenecks in the hardware architecture that limit the processing capabilities of the architecture.
In early or more simple hardware architectures, a single processor core can be configured to access from associated memory, a single instruction or operand per instruction cycle. The processor can operate based on a clock signal and each instruction cycle can be one or more clock cycles.
In such a simple hardware architecture, the clock speed can be increased to increase the execution time for the application. However, there are practical limitations to clock rates, although presently available processors can operate at clock rates on the order of hundreds of megahertz and may include internal multipliers that increase the effective clock rate to several gigahertz.
More complicated architectures can include multiple processing paths that are configured in parallel. In a basic variation of the multiple path architecture, each processing path can operate independently of any other processing path and each processing path can have hardware dedicated to the particular path.
The program execution time in an architecture having multiple processing paths can be improved in part by increasing the clock rates of the processing paths. Additionally, the program execution time may be improved by efficient scheduling of instructions executed in each individual processing path. Thus, because the compiler schedules the low level instructions translated from higher level code, the operation of the compiler can have significant impact on the execution time of an application or program.
It is desirable to optimize the allocation of resources consumed and the scheduling of instructions in parallel processing applications in order to optimize the execution of the application. One benefit of such optimization can be a decrease in the execution time of the application with no hardware changes.